Ph. D. - University of Rennes 1 electronics, Signal processing and telecommunications in 2013
The use of hardware accelerators offers good optimization possibilities during system conception.
These accelerators are used to unload a processor of repetitive and heavy tasks.
Dynamic Reconfiguration of accelerators allows a time sequence of blocs and leads to reduce area.
However, nowadays it is difficult to have an estimation of conception choices effects on power consumption, especially.
Swung between overcost and gain for execution time and energy, dynamic reconfiguration is in addition difficult to implement.
The main objective of this thesis is to build power consumption models of reconfigurable components, in particular FPGAs, which will enable the designer in his implementation choices. Power consumption of tasks is modeled following different level of characteristics (memory access, area, computations...)
Models will be used by a scheduler (OS) to make implementation choices (reconfiguration, hardware and software execution) according to energy or real time constraints.
- Partial Reconfiguration
- Power and energy measurement
- Power/energy estimation and reduction
- Electronic cards prototyping