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Robin Bonamy

(français)

Presentation

2014-2015 Post-doc

2013-2014 Research engineer

Ph. D. - University of Rennes 1 electronics,  Signal processing and telecommunications in 2013

Thema : Energy consumption optimization and modeling for reconfigurable devices

Advisors : Daniel Chillet, Olivier Sentieys and Sébastien Bilavarn

Research team CAIRN-Lannion (France), University of Rennes 1 - IRISA


Work


The use of hardware accelerators offers good optimization possibilities during system conception.
These accelerators are used to unload a processor of repetitive and heavy tasks.
Dynamic Reconfiguration of accelerators allows a time sequence of blocs and leads to reduce area.

However, nowadays it is difficult to have an estimation of conception choices effects on power consumption, especially.

Swung between overcost and gain for execution time and energy, dynamic reconfiguration is in addition difficult to implement.

The main objective of this thesis is to build power consumption models of reconfigurable components, in particular FPGAs, which will enable the designer in his implementation choices. Power consumption of tasks is modeled following different level of characteristics (memory access, area, computations...)

Models will be used by a scheduler (OS) to make implementation choices (reconfiguration, hardware and software execution) according to energy or real time constraints.

Skills

  • FPGA
  • Partial Reconfiguration
  • Power and energy measurement
  • Power/energy estimation and reduction
  • Electronic cards prototyping

Publications - Communications

  • R. Bonamy, Modélisation de la consommation des architectures reconfigurables et de la reconfiguration dynamique,  CAIRN team seminar 2010, 1-3 December 2010, Erdeven (slides)
  • R. Bonamy, Modélisation et Optimisation de la Consommation dans Les FPGA, Comité de suivi de thèse,  April, 26th 2011, Lannion (slides)
  • R. Bonamy, D. Chillet, O. Sentieys and S. Bilavarn, Towards a Power and Energy Efficient Use of Partial Dynamic Reconfiguration,  GDR Soc-Sip seminar, 15-17 June 2011, Lyon (poster)
  • R. Bonamy, Modélisation et Optimisation de la Consommation dans Les FPGA, MCSOC days (LEAT), 29-30 June 2011, Sophia-Antipolis (slides) (paper)






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Last update : March 2nd 2015
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